Senior Digital System Design Engineer:
Implement logic design on Integrated circuits, be familiar with Verilog, RTL, Synthesis and verification procedures and tools. Familiar with use and of programming of FPGA.
Minimum requirement
· BS with minimum 8 year or MS with minimum 6 years’ experience on digital design and verification.
· Experience with IC logic design, simulation and verification.
· Implementation experience with arithmetic functions.
· Implementation or verification experience of high-speed bus interface and IP
· Lab bring-up or testing experience
Preferred experience with one or more of the items listed below
· Experience with synthesis (Synopsys or Cadence tool), STA, timing closure, and tapeout procedure.
· Experience with DSP module based on Matlab or C model.
· Design & verification experience with high-speed interface or protocol such as DDR, Serdes, Ethernet, or USB.
· Embedded processor experience
· DFT or scan insertion experience
· Experience with interface design with analog modules, such as ADC and PLL.
· Experience with FPGA implementation.
· Board design or verification experience.
· C, Python, or Assembly programming experience