Uhnder has developed the world’s first automotive digital Radar on Chip (RoC). Sensors based on Uhnder’s Digitally Coded Modulation (DCM) technology achieve new and unprecedented levels of performance for advanced driver assistance systems (ADAS) and autonomous driving solutions. Founded in 2015, its main engineering operations center is in Austin, Texas, USA with design facilities in India and China. MulticoreWare is facilitating the Uhnder operations in India.
Using a combination of advanced CMOS and Digital Code Modulation (DCM) technology to deliver the industry’s first digital automotive Radar-On-Chip (ROC), Uhnder’s approach and technology is transforming the automotive industry by changing the way radars work with significant improvements in performance with the additional benefits of smaller size, lower power and cost.
As a Design Verification Engineer at UhDC, you will verify the design and implementation of a leading SoC design for the automotive space. In this position you will be a member of the verification team responsible for signal processing pipeline verification – spanning the following areas: ASIC design, architecture, golden models and micro-architecture.
• BS / MS with 3-6 years of experience
• Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies
• Exposure to design and verification tools (VCS or equivalent simulation tools, debug tools like Debussy, GDB)
• Experience with test bench environments for unit and system level verification
• Good debugging and problem-solving skills
• Good communication skills and ability & desire to work as a team player are a must
• Leading the verification effort of a complex chip, sub-system and/or blocks
• Define accelerator pipeline level verification strategies, test planning, and develop all necessary tools and scripts to enable system-level testing in an automated fashion
• Work with the block/core teams to develop re-usable test cases
• Developing and integrating verification environment components
• Developing test plans from functional specifications
• Writing, executing and debugging test
• Need to have experience in System Verilog and either UVM (preferred) or OVM
• Experience in verifying math intensive Signal Processing pipelines (Filters, FFT etc.)
• Must have hands-on experience and strong knowledge in test bench automation, industry standard bug tracking, and regression mechanisms
• In-depth knowledge in SoC architecture, including CPUs (preferably ARM), memory subsystems and accelerators, multi-domain clocking, and bus & interconnect structures (preferably as AHB and AXI)
• Must have excellent system debug skills
• Excellent oral and written communication skills & ability to work in a team environment