As a Verification Engineer, you will verify the design and implementation of a leading System-on-Chip (SoC) design. In this position, you will be a member of the verification team responsible for pre-silicon design verification, spanning the following areas: design, architecture, golden models, and micro-architecture. Responsibilities will also include post-silicon bring up and debug and test vector generation.

 

Essential Functions

•             Creation and execution of verification test plans from internal specifications, external IP, and in coordination with architects and designers

•             Creation and deployment of automated flows for block and chip level verification and coverage collections, for Datapath, DSP and SoC subsystems

•             Develop Verilog, System Verilog, and UVM test environments, including analog component models and external components/models

•             Architect, design, and troubleshoot UVM verification components, environments, and scripts

•             Work with Analog and Digital team members to debug failures, manage bug tracking, and achieve the high coverage needed for automotive products

•             Hold detailed verification reviews and set standards for coding quality

•             Integrate 3rd party VIP and testcase into system level suites

•             Test planning development and regression setup using either Python/Perl/Tcl scripts

•             Planning, execution, and debug of simulations for functional verification

•             Work closely on pre-tape-out gate level verification using simulation and emulation platforms, as well as silicon bring-up, debug, and optimization

Required Education and Experience:

•             BS or MS degree in EE/CS focused on VLSI Design

•             Course work should include programming courses in C/C++, VLSI Design/Computer architecture/

•             Knowledge of ARM/DSP Cores is a plus.

•             Verilog/VHDL/System Verilog design experience is a plus