Verification Lead/Manager

Summary/Objective

Uhnder has developed the world’s first automotive digital Radar-on-Chip (RoC).  Sensors based on Uhnder’s Digital Coded Modulation (DCM) technology achieve new and unprecedented levels of performance for advanced driver assistance systems (ADAS) and autonomous driving solutions.  Founded in 2015, Uhnder’s main engineering operations center is in Austin, Texas, with design facilities in India and China.  

Uhnder’s approach and technology is transforming the automotive industry by changing the way radars work, with significant improvements in performance and the additional benefits of smaller size and lower power and cost. 

As Uhnder’s Verification Lead/Manager, you will lead a design verification team focused on building functional verification infrastructure for directed and constrained - randomized tests. In this position, you will be responsible for the full chip verification, spanning the following areas: full life cycle of verification (from planning to test execution, including collecting and closing coverage), conducting/participating in test plan and test reviews, developing verification components/tests and triage failures, project scheduling, mentoring, and providing technical guidance.

Essential Functions

  • Provide technical leadership and management of verification team
  • Develop strategies to insure the efficient creation and execution of verification plans from internal specifications, external IP, and in coordination with architects and designers 
  • Lead creation and deployment of automated flows for block and chip level verification and coverage collections, for Datapath, DSP and SoC subsystems
  • Manage team execution of test plan development and test regressions
  • Architect, design, and troubleshoot UVM verification components, environments, and scripts
  • Work with Analog and Digital team members to debug failures, manage bug tracking, and achieve the high code, functional and system level coverage needed for automotive products 
  • Coordinate and manage verification review procedures/standards 
  • Test planning development and regression setup using either Python/Perl/Tcl scripts
  • Lead planning, execution, and debug of gate level simulations for functional, DFT verification and power analysis 
  • Plan, develop, and deploy FPGA based verification systems (Xilinx/Protium) to augment and complete verification requirements and support early software development
  • Work closely on pre-tape-out verification using simulation and emulation platforms, as well as silicon bring-up, debug, and optimization

 

Required Education and Experience:

  • BS degree in EE/CS with 15+ years of relevant experience 
  • Experience leading verification teams/efforts
  • Advanced knowledge of HVL methodology (UVM/OVM/VMM)
  • Solid verification skills in problem solving, constrained random testing, and debugging
  • Knowledge of industry standard interfaces (Gigabit Ethernet, UART, I2C, QSPI)
  • Expert in System Verilog, UVM – should have independently created UVM based verification environments from scratch
  • Experience in working with multi-site development teams 
  • Proven success in unit, sub-system, and SoC verification
  • Hands on experience with Gate level simulations, SDFs, and Gate level simulation debug
  • Experience with industry standard verification tools, VIP/AVIP integration, and configuration in testbenches
  • Able to understand and debug RTL code
  • Experience writing scripts in Perl/Python
  • Excellent communication skills and the desire to be a team player  
  • Willingness and drive to take on diverse challenges
  • Exposure to ISO 26262 Functional Safety verification is a plus
  • Experience with FPGA based verification/development with Protium is a plus 
  • Matlab experience is a plus
  • Experience with System Verilog Assertions (SVA) is a plus
  • Programming experience in C/C++ is a plus