Summary/Objective

Uhnder has developed the world’s first automotive digital Radar on Chip (RoC).  Sensors based on Uhnder’s Digitally Coded Modulation (DCM) technology achieve new and unprecedented levels of performance for advanced driver assistance systems (ADAS) and autonomous driving solutions.  Founded in 2015, its main engineering operations center is in Austin, Texas, USA with design facilities in India and China.

As a Design PPA Optimization Engineer you will join a team of industry experts spanning mixed-signal, RF, digital, systems and software experts to develop the next generation of electronics surrounding us and impacting us in our everyday lives.  You will focus on optimizing the Performance, Power and Area (PPA) results of designs by focusing on the synthesis stage of the design process.  This is a very key stage in the IP development and integration efforts for the RoC products and is key to allowing the designs to meet the product’s PPA goals.  You will work closely with the uArch, design and physical design teams to facilitate evaluation of the impact of design choices and on PPA results and to support timing analysis of the design from RTL through to tapeout. This role will also have responsibility for different aspects of the overall RTL QA efforts : Lint, CDC, RDC, Constraint validation, DFT sanity checks, Formal Verification, etc.

 

Essential Functions

·         Synthesis of IP blocks from both internal and external design teams

·         Evaluation of PPA tradeoffs at block and full chip levels

·         Development of IP-level and chip-level timing constraints

·         Synthesis-driven optimizations of designs to improve PPA results

·         Development of synthesis flows to support advanced design optimizations.

·         Development and integration of flow support for advanced DFT solutions.

·         Work with RTL QA tools to analyze IP and optimize the analysis flows

 

 

Required Education and Experience:

·         BS in Electrical Engineering, MS preferred

·         5 or more years of relevant industry experience

·         Experience with synthesis flows

·         Knowledge of clock and reset domain crossing methodologies

·         DFT insertion and validation flows

·         Understanding of the timing challenges related to external interfaces.

·         Experience addressing PPA related implementation challenges

·         Experience with low-power design and validation techniques

·         Good communication skills

·         Fluent in English

·         Automotive experience a plus

·         Experience with ISO 26262 a plus