Timing Analysis Engineer

Summary/Objective

Uhnder has developed the world’s first automotive digital Radar on Chip (RoC).  Sensors based on Uhnder’s Digitally Coded Modulation (DCM) technology achieve new and unprecedented levels of performance for advanced driver assistance systems (ADAS) and autonomous driving solutions.  Founded in 2015, its main engineering operations center is in Austin, Texas, USA with design facilities in India and China.

As a Timing Analysis Engineer you will join a team of industry experts spanning mixed-signal, RF, digital, systems and software experts to develop the next generation of electronics surrounding us and impacting us in our everyday lives.  You will focus on optimizing the synthesizing of the IP developed for and integrated into the  RoC architectures to meet the product’s Performance/Power/Area goals.  You will work closely with the design and physical design teams to facilitate evaluation of the impact of design choices and on PPA results and to support timing analysis of the design from RTL through to tapeout.

 

Essential Functions

•      Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation).

•      Develop and maintain methodology and flows related to timing verification and closure.

•      Generation of block and full chip timing constraints.

•      Analyze timing reports and utilize scripting techniques to develop insights and drive rapid timing closure.

•      Support digital chip integration work and flows.

 

 

Required Education and Experience:

·         BS in Electrical Engineering, MS preferred

·         5 or more years of relevant industry experience

  • Expertise in STA tools (such as Tempus or Primetime) and methodologies for timing closure with a good understanding of OCV, noise and cross-talk effects on timing.
  • Familiarity with all aspects of timing closure of high-performance, mixed-signal SoCs in advanced process technology nodes (16nm and below).
  • Knowledge of timing corners/modes and process variations.
  • Knowledge of CDC/RDC issues and associated verification methology
  • Proficient in scripting languages (Tcl, Python, …).
  • Strong communication skills are a pre-requisite as the candidate will interface with a lot of different groups (e.g. digital design, verification, DFT, physical design, etc.).
  • Selfr and highly motivated.
  • Familiarity with RTL, synthesis, logic equivalence, DFT, floor-planning, and backend related methodology and tools a plus.

·         Knowledge of low-power techniques including clock gating, power gating and multi-voltage designs a plus

·         Good communication skills

·         Fluent in English

·         Automotive experience a plus

·         Experience with ISO 26262 a plus

 

Location:

Austin, TX