As a Senior Verification Engineer, you will verify the design and implementation of a leading System-on-Chip (SoC) design for the automotive space. In this position, you will be a member of the verification team responsible for full chip verification, spanning the following areas: ASIC design, architecture, golden models, and micro-architecture.

Essential Functions

  • Creation and execution of verification plans from internal specifications, external IP, and in coordination with architects and designers 
  • Creation and deployment of automated flows for block and chip level verification and coverage collections, for Datapath, DSP and SoC subsystems
  • Develop Verilog, System Verilog, and UVM test environments, including analog component models and external components/models
  • Architect, design, and troubleshoot UVM verification components, environments, and scripts
  • Work with Analog and Digital team members to debug failures, manage bug tracking, and achieve the high code, functional and system level coverage needed for automotive products 
  • Hold detailed verification reviews and set standards for coding quality 
  • Integrate 3rd party VIP and testcase into system level suites
  • Test planning development and regression setup using either Python/Perl/Tcl scripts
  • Planning, execution, and debug of gate level simulations for functional, DFT verification and power analysis 
  • Plan, develop, and deploy FPGA based verification systems (Xilinx/Protium) to augment and complete verification requirements and support early software development
  • Work closely on pre-tape-out verification using simulation and emulation platforms, as well as silicon bring-up, debug, and optimization
  • Work as part of an agile Digital team to ensure first silicon success

 

Required Education and Experience:

  • BS degree in EE/CS with ~8 years of relevant experience 
  • Advanced knowledge of HVL methodology (UVM/OVM/VMM)
  • Solid verification skills in problem solving, constrained random testing, and debugging
  • Knowledge of industry standard interfaces (Gigabit Ethernet, UART, I2C, QSPI)
  • Expert in System Verilog, UVM – should have independently created UVM based verification environments from scratch
  • Experience in working with multi-site development teams 
  • Proven success in unit, sub-system, and SoC verification
  • Hands on experience with Gate level simulations, SDFs, and Gate level simulation debug
  • Experience with industry standard verification tools, VIP/AVIP integration, and configuration in testbenches
  • Able to understand and debug RTL code
  • Experience writing scripts in Perl/Python
  • Excellent communication skills and the desire to be a team player  
  • Willingness and drive to take on diverse challenges
  • Exposure to ISO 26262 Functional Safety verification is a plus
  • Experience with FPGA based verification/development with Protium is a plus 
  • Matlab experience is a plus
  • Experience with System Verilog Assertions (SVA) is a plus
  • Programming experience in C/C++ is a plus