Uhnder (http://www.uhnder.com) has developed the world’s first automotive digital Radar-on-Chip (RoC). Sensors based on Uhnder’s Digital Coded Modulation (DCM) technology achieve new and unprecedented levels of performance for advanced driver assistance systems (ADAS) and autonomous driving solutions. Founded in 2015, Uhnder’s Silicon development engineering operations are in Austin, Texas, US and Chennai, TN India.

Uhnder’s approach and technology is transforming the automotive industry by changing the way radars work, with significant improvements in performance and the additional benefits of smaller size and lower power and cost. 

Uhnder’s Verification Team is responsible for the verification of IP, Modules, Sub-Systems, System-on-Chip (SoC) (Functional Verification (RTL/PARTL/WRTL); Gate Level Simulation/Verification (GLS) and all aspects of Pre-Silicon Verification); Application & Use Case Verification (in terms of performance, throughput, latency, bandwidth and system use cases), Functional Vector Generation as well as Silicon Bring-up.

 

As a member of the Verification team, one will/can participate, in all the above activities, based on the stage of the design and to achieve a successful one-pass silicon. Uhnder is currently looking to add Verification Engineers with various levels of experience: 10+ years for Senior, 5-10 years for Mid-Level, & 2-5 years for Junior Levels as well as New College Grad (NCG). Opportunities exist in Austin (Uhnder worldwide HQ) & Chennai and remote work from other sites (such as Benguluru & Dallas) is possible

 

Essential Functions

 

·         Create and execute verification plans from internal specifications, external IP, and in collaboration with system architects and designers. 

·         Develop tests to achieve functional and coverage goals/targets for the design.

·         Create and deploy automated flows for Unit/Block and Chip level verification and for coverage metrics collection, for Datapath, Cores (DSP/ARM) and SOC subsystems.

·         Develop Synthesizable Verilog, System Verilog Components for Test Bench, and/or integrate UVM components, including analog component models and external components/models into the testbench

·         Architect, design, and troubleshoot UVM Components, Bus Functional Models (BFM’s), environments,

·         Write Checkers, develop monitors, maintain scoreboards as needed/appropriate.

·         Work with Analog and Digital team members to debug failures, manage bug tracking, and achieve the high code, functional and system level coverage needed.

·         Hold detailed verification plan reviews with cross functional system and design teams.

·         Set & practice standards for coding quality.

·         Integrate 3rd party VIP & models into Test Bench and testcases into system level test suites

·         Develop scripts in Python/Perl/TCL/Shell scripts to achieve the objectives

·         Plan, execute and debug of gate level simulations for functional, and power analysis/estimation

·         Plan, develop, and deploy FPGA based verification systems (Xilinx/Protium) to augment and complete verification requirements and support early software development

·         Work closely on pre-tape-out verification using simulation and emulation platforms, as well as silicon bring-up, debug, and optimization.

·         Develop/Debug Functional Test Vectors for ATE (Automatic Test Equipment)

 

 

Required Education and Experience:

 

·         BS/MS degree in EE/CS

·         Knowledge in industry standard processor cores from ARM/Tensilica and others

·         Knowledge in industry standard protocols such as AMBA/AXI

·         Knowledge of industry standard peripheral interfaces (DDR, Gigabit Ethernet, UART, I2C, QSPI etc.)

·         Ability to read/understand and debug Verilog/System Verilog/VHDL RTL code is expected.

·         Experience in Verilog, System Verilog, UVM, OVM, VMM

·         Programming experience in C/C++

·         MATLAB experience is a plus

·         Experience with System Verilog Assertions (SVA) is a plus

·         Solid verification skills in problem solving, as well as targeted & constrained random testing and debugging

·         Hands on experience with Gate level simulations (GLS).

·         Knowledge of standard library components such as synchronizers/clock cells/memories is expected.

·         Knowledge & adherence of revision control tools/mechanisms.

·         Experience with industry standard verification tools, VIP/AVIP integration, and configuration in synthesizable testbenches

·         Experience writing scripts in Perl/Python/Shell/TCL

·         Experience & Willingness to working with multi-site development teams 

·         Excellent communication skills and the desire to be a part of cohesive multiply talented diverse team located at multiple sites.

·         Willingness and drive to take on diverse challenges

·         Exposure to ISO 26262 Functional Safety verification is a plus

·         Experience with FPGA based verification/development with Protium is a plus.