Using a combination of advanced CMOS and Digital Code Modulation (DCM) technology to deliver the industry’s first digital automotive Radar-on-Chip (RoC), Uhnder’s approach and technology is transforming the automotive industry by changing the way radars work with significant improvements in performance and the additional benefits of smaller size and lower power and cost. 

As a Senior Digital Staff Engineer, you will join a team of digital architecture, design and verification experts in the architecture/design and verification of a complex System-on-Chip (SoC) with extensive Signal Radar Processing. We are looking for a self-driven individual who can work well with architects, HW, and SW developers to quickly resolve blocking issues.

Essential Functions

  • Digital Architecture/Design of high throughput Signal Processing Blocks (from Matlab model to full digital design)
  • SoC / System Validation and Emulation using an FPGA accelerator including System Performance Analysis 
  • Chip bring-up and system validation on actual silicon
  • Develop and modify infrastructure for automated use-case testing, data gathering, and analysis
  • Work with Systems, Analog, and Digital team members to debug failures, manage bug tracking, and achieve the high code, functional and system level coverage needed for automotive products 
  • Hold detailed design reviews and set standards for coding quality 
  • Integrate 3rd party IP
  • Plan, develop, and deploy FPGA based verification systems (Xilinx/Protium) to augment and complete verification requirements and support early software development
  • Work as part of an agile Digital team to ensure first silicon success


Required Education and Experience:

  • BS degree in EE/CS with more than 15 years of relevant experience 
  • Expertise in ASIC Architecture/Design and Verification of SoC and Digital Signal Processing Blocks
  • Knowledge of industry standard interfaces (Gigabit Ethernet, UART, I2C, QSPI)
  • Experience in working with multi-site development teams 
  • Proven success in unit, sub-system, and SoC verification
  • Hands on experience with Gate level simulations, SDFs, and Gate level simulation debug
  • Experience with System Performance Analysis and debugging system level issues
  • Experience writing scripts in Perl/Python
  • Experience with ISO 26262 Functional Safety
  • Excellent communication skills and the desire to be a team player
  • Willingness and drive to take on diverse challenges
  • Experience with FPGA based verification/development with Protium is a plus 
  • Matlab experience is a plus
  • Programming experience in C/C++ is a plus



Chris Chalberg


Innovative People Experts, LLC