Movandi has made a big impact on 5G in a short amount of time — from foundational research and innovative modular, high efficiency mmWave system design to the introduction of our BeamXR 5G system that delivers improvements in performance, coverage, and latency to connect 5G everywhere. Now more than ever, 5G--supported by Movandi technology--is becoming an integral part of the telecommunications landscape. And we’re only getting started.

 

At Movandi we work as a team. We like hard problems and solving them with the sharpest people. Are you looking to make a difference on the future of technology? At Movandi, you will help solve the growing challenges of deploying 5G millimeter wave networks. You will make an impact.

About the Role

We’re looking for a graduate Digital Design Engineer to join our hardware team and help build high‑performance digital systems. You’ll design, simulate, and verify RTL modules in VHDL or Verilog, contribute to FPGA/ASIC development, and collaborate across hardware, embedded software, and verification to deliver reliable, testable designs.

What You’ll Do

  • RTL design: Implement synthesizable, well‑structured RTL in VHDL or Verilog for FPGA or ASIC targets.

  • Simulation & verification: Write testbenches, run simulations (e.g., ModelSim/Questa, Xcelium, VCS), debug waveforms, and close functional coverage.

  • Documentation: Produce clear design specs, interface docs, and verification plans; contribute to design reviews.

  • Lab bring‑up: Assist with hardware validation and debug using oscilloscopes, logic analyzers, JTAG, and boards.

  • Quality & processes: Use version control, issue trackers, and CI. Follow coding guidelines and contribute to continuous improvement.

Must‑Have Qualifications

  • Degree: Bachelor’s in Electrical/Electronic Engineering, Computer Engineering, or related field (recent graduate).

  • HDL proficiency: VHDL or Verilog Comfortable writing synthesizable RTL and basic testbenches.

  • Digital fundamentals: Strong grasp of synchronous design, FSMs, pipelining, resets, clock domains, CDC, and metastability.

  • Tools familiarity: At least one of: Vivado, Quartus, Radiant or Diamond for FPGA or exposure to Synopsys/Cadence/Mentor/Siemens toolchains in coursework.

  • Timing & constraints: Basic understanding of STA, timing paths (setup/hold), and constraint files (SDC/XDC).

  • Scripting & workflow: Exposure to Python/Tcl/Make for automation. Comfortable in Linux development environments.

  • Communication & teamwork: Clear written/spoken communication, collaborative mindset, willingness to learn.

Nice‑to‑Have (Preferred)

  • Experience with UVM/OVM/SystemVerilog verification methodologies.

  • Knowledge of AXI/AHB, SPI/I²C/UART, PCIe/Ethernet/DDR interfaces.

  • Familiarity with DSP blocks, clocking resources, and power/performance/area trade‑offs.

  • Exposure to C/C++ for embedded integration or firmware bring‑up.

  • Hands‑on with board‑level debug, schematics, or lab instrumentation.

Tools & Technologies

  • HDLs: VHDL, Verilog (SystemVerilog for verification is a plus).

  • FPGA: Xilinx Vivado, Intel Quartus, Lattice Radiant; IP integrators and constraint management.

  • ASIC: Synopsys Design Compiler, Cadence Genus/Innovus, Siemens Calibre (exposure).

  • Simulation/Verification: ModelSim/Questa, Synopsys VCS, Cadence Xcelium, cocotb/UVM (optional).

  • Workflow: Git, CI/CD, Python/Tcl scripting, Linux shell; issue tracking (Jira/GitHub).