The Verification Engineer’s primary job function is to work with other team members to develop test plans and verify the RTL designs.

Requirements:

1.       B.S. or M.S. in Electrical Engineering or equivalent

2.       5 to 10 years of design verification experience

3.       Experience with verification of modules from test plan to regression.

4.       Knowledge of Verilog, SystemVerilog, UVM, and Synopsys VCS